Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and particularly to a memory device and a method of fabricating the same.
Description of Related Art
In order to improve the integration density of dynamic random access memory (DRAM) to speed up the operation speed of devices and meet the consumer's requirement of miniaturization of electronic devices, buried word line DRAM has been developed to meet the above requirements in recent years. However, with the increase of the integration density of memory, the spacing between word lines and the isolation structure of the memory array may continue reducing resulted in various undesirable influences, such as cell-to-cell leakage, interference between word lines (also called as row hammer), read/write time failure (twr failure), retention failure, bit line coupling failure, and the like.
Currently, for the interference between word lines, an isolation structure deeper than the buried word lines is a way used to improve the above problems. As a result, it is necessary to change the original process of the isolation structure. That is, one lithography process of forming the word lines and the isolation structure simultaneously changes into at least two lithography processes. One is for fabricating the deeper isolation structure while the other one is for fabricating the buried word line between the isolation structures.
However, in the prior art, alignment issue tends to happen by using multi-lithography processes to form the isolation structure and the capacitor contact respectively. The alignment issue becomes worse with the reduction of device size. For example, it may cause a reduction of a contact area between an active area (e.g. source/drain region) and a capacitor contact. Since the contact area between the active area and the capacitor contact becomes smaller, resistance between the active area and the capacitor contact increases and thereby resulted in read/write time failure. Therefore, how to develop a method of fabricating a memory device to improve the problem of the reduction of the contact area between the active area and the capacitor contact caused by a misalignment in a lithography process becomes an important issue.